Hardware-Based Text-to-Braille Translator
Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray · 2006 · Proceedings of the 8th International ACM SIGACCESS Conference on Computers and Accessibility (Assets '06) · doi:10.1145/1168987.1169029
Summary
This paper describes the implementation of a text-to-Braille translator in hardware using Field-Programmable Gate Arrays (FPGAs), as an alternative to the software-based translators that dominate the market. The translator implements Paul Blenkhorn's algorithm for converting text into Standard English Braille (Grade 2), which uses contractions to represent common letter combinations and words more efficiently than the letter-by-letter Grade 1 Braille. The algorithm uses a decision table with input classes, states, and rules: each rule has the format "left context [focus] right context = input text" where the focus, left context, and right context determine how characters should be translated. The hardware architecture consists of eight sub-blocks within a translating block: a data controller, translating controller, find-entry block, look-up table, output-rule block, focus-check, right-context-check, left-context-check, and load-translated-codes block. The system receives ASCII text via an RS-232 serial interface, processes the translation five words at a time, and outputs the translated Braille codes back to a PC. The design was described using VHDL (Very high speed Hardware Description Language) in a hierarchical top-down methodology and implemented on a Xilinx Virtex-II FPGA development board.
Key findings
Testing confirmed that the hardware translator produces the same results as commercial software-based Braille translators, validating the accuracy of the hardware implementation. The FPGA processes text at 57,600 baud through its serial interface, translating at 4,300 bauds with output sent back to the PC. A key advantage of the hardware approach is that the translation runs faster than the serial communication channel can deliver data, meaning the translation process is not the bottleneck — the PC's communication interface is. This suggests that in embedded applications where the translator is directly connected to a Braille output device without a PC intermediary, throughput could be significantly higher. The authors identify several improvements for future versions: incorporating the system into an embedded, high-volume production version using application-specific integrated circuits (ASICs); supporting multi-language Braille translation by loading different language look-up tables stored in flash memory; and creating a standalone component that does not require a PC, making Braille translation available for portable and embedded assistive devices.
Relevance
This paper demonstrates an approach to making Braille translation available as a dedicated hardware component rather than requiring a full computer running translation software. For assistive technology design, this has practical implications: a hardware translator could be embedded directly into Braille displays, embossers, or portable reading devices, reducing complexity, cost, and power consumption. The multi-language capability proposed — swapping look-up tables in flash memory for different languages — addresses a real need, as Braille contractions differ across languages and most software translators require separate installations for each. While FPGA-based assistive technology remains niche, the underlying principle of moving accessibility processing into dedicated hardware is relevant to modern embedded systems and IoT devices designed for accessibility.
Tags: braille · braille translation · FPGA · hardware · embedded systems · assistive technology
Standards referenced: ASCII